How To Get Certain Bits Of A Register

Digital Circuits - Shift Registers

Nosotros know that one flip-bomb tin store 1-bit of data. In gild to store multiple bits of information, we require multiple flip-flops. The group of flip-flops, which are used to concur (store) the binary data is known as register.

If the register is capable of shifting bits either towards right hand side or towards left mitt side is known as shift register. An 'Northward' flake shift annals contains 'N' flip-flops. Following are the four types of shift registers based on applying inputs and accessing of outputs.

Serial In − Serial Out shift annals
Series In − Parallel Out shift register
Parallel In − Serial Out shift register
Parallel In − Parallel Out shift register

Serial In − Series Out (SISO) Shift Register

The shift register, which allows serial input and produces serial output is known equally Serial In – Series Out (SISO) shift register. The block diagram of 3-bit SISO shift register is shown in the following figure.

SISO

This block diagram consists of iii D flip-flops, which are cascaded. That ways, output of i D flip-flop is continued every bit the input of side by side D flip-flop. All these flip-flops are synchronous with each other since, the aforementioned clock bespeak is applied to each i.

In this shift register, we tin send the bits serially from the input of left nearly D flip-bomb. Hence, this input is also called as series input. For every positive edge triggering of clock signal, the data shifts from one stage to the side by side. So, nosotros tin receive the $.25 serially from the output of right most D flip-flop. Hence, this output is also chosen as serial output.

Example

Let us run across the working of 3-bit SISO shift annals by sending the binary information "011" from LSB to MSB serially at the input.

Assume, initial condition of the D flip-flops from leftmost to rightmost is $Q_{two}Q_{ane}Q_{0}=000$. Nosotros tin can understand the working of three-bit SISO shift register from the following table.

No of positive edge of Clock	Series Input	Q₂	Q₁	Q₀
0	-	0	0	0
i	i(LSB)	one	0	0
2	1	i	one	0
3	0(MSB)	0	1	i(LSB)
four	-	-	0	one
5	-	-	-	0(MSB)

The initial condition of the D flip-flops in the absenteeism of clock betoken is $Q_{2}Q_{1}Q_{0}=000$. Hither, the serial output is coming from $Q_{0}$. Then, the LSB (1) is received at 3^rd positive border of clock and the MSB (0) is received at v^th positive edge of clock.

Therefore, the three-bit SISO shift register requires five clock pulses in gild to produce the valid output. Similarly, the N-scrap SISO shift register requires 2N-1 clock pulses in lodge to shift 'N' bit information.

Serial In - Parallel Out (SIPO) Shift Annals

The shift register, which allows serial input and produces parallel output is known as Serial In – Parallel Out (SIPO) shift annals. The block diagram of 3-flake SIPO shift register is shown in the following figure.

SIPO

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the aforementioned clock signal is practical to each one.

In this shift register, we tin can send the bits serially from the input of left near D flip-flop. Hence, this input is likewise called as serial input. For every positive edge triggering of clock bespeak, the information shifts from i stage to the next. In this case, nosotros can access the outputs of each D flip-flop in parallel. And then, nosotros will go parallel outputs from this shift register.

Example

Let usa meet the working of 3-bit SIPO shift register by sending the binary information "011" from LSB to MSB serially at the input.

Presume, initial condition of the D flip-flops from leftmost to rightmost is $Q_{2}Q_{i}Q_{0}=000$. Here, $Q_{ii}$ & $Q_{0}$ are MSB & LSB respectively. We tin can empathize the working of 3-scrap SIPO shift register from the following tabular array.

No of positive edge of Clock	Serial Input	Q₂(MSB)	Q₁	Q₀(LSB)
0	-	0	0	0
1	1(LSB)	ane	0	0
2	1	1	1	0
3	0(MSB)	0	1	one

The initial status of the D flip-flops in the absence of clock bespeak is $Q_{two}Q_{one}Q_{0}=000$. The binary information "011" is obtained in parallel at the outputs of D flip-flops for third positive edge of clock.

And so, the iii-scrap SIPO shift annals requires three clock pulses in club to produce the valid output. Similarly, the N-bit SIPO shift annals requires Due north clock pulses in gild to shift 'Due north' scrap information.

Parallel In − Serial Out (PISO) Shift Register

The shift register, which allows parallel input and produces serial output is known equally Parallel In − Serial Out (PISO) shift register. The cake diagram of three-bit PISO shift annals is shown in the following figure.

PISO

This excursion consists of three D flip-flops, which are cascaded. That ways, output of one D flip-flop is connected equally the input of adjacent D flip-flop. All these flip-flops are synchronous with each other since, the same clock betoken is practical to each one.

In this shift annals, we can use the parallel inputs to each D flip-bomb past making Preset Enable to 1. For every positive edge triggering of clock betoken, the data shifts from ane stage to the next. And then, nosotros will get the serial output from the right virtually D flip-flop.

Example

Let us see the working of iii-bit PISO shift register past applying the binary data "011" in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial condition of the D flip-flops from leftmost to rightmost will be $Q_{two}Q_{1}Q_{0}=011$. Nosotros can empathise the working of 3-fleck PISO shift register from the following table.

No of positive edge of Clock	Q₂	Q₁	Q₀
0	0	one	1(LSB)
1	-	0	1
2	-	-	0(LSB)

Here, the serial output is coming from $Q_{0}$. Then, the LSB (1) is received before applying positive edge of clock and the MSB (0) is received at two^nd positive edge of clock.

Therefore, the three-bit PISO shift register requires two clock pulses in order to produce the valid output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in order to shift 'Northward' scrap information.

Parallel In - Parallel Out (PIPO) Shift Register

The shift register, which allows parallel input and produces parallel output is known equally Parallel In − Parallel Out (PIPO) shift annals. The block diagram of iii-flake PIPO shift register is shown in the post-obit effigy.

PIPO

This circuit consists of three D flip-flops, which are cascaded. That means, output of ane D flip-bomb is connected as the input of side by side D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each i.

In this shift annals, we tin use the parallel inputs to each D flip-bomb by making Preset Enable to 1. We can utilize the parallel inputs through preset or clear. These two are asynchronous inputs. That means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs. In this case, the consequence of outputs is independent of clock transition. So, we will get the parallel outputs from each D flip-flop.

Case

Let us see the working of 3-flake PIPO shift register by applying the binary data "011" in parallel through preset inputs.

Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from leftmost to rightmost will be $Q_{ii}Q_{1}Q_{0}=011$. And so, the binary information "011" is obtained in parallel at the outputs of D flip-flops before applying positive edge of clock.

Therefore, the 3-bit PIPO shift annals requires zilch clock pulses in order to produce the valid output. Similarly, the N-flake PIPO shift annals doesn't crave any clock pulse in order to shift 'Due north' bit data.